# Reference Frequency Divider

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and 5. The purpose of the divide-by-ten prescaler is to lower the vco frequency a bit so that the programmable counter can function reliably. The output of the prescaler is 3.5 to 3.799 MHz, and this feeds the programmable ordivide-by-n counter. I used an MC12013P IC for the divide-by-ten circuit; however, almost any prescaler IC will work.

Looking at the circuit, transistor Q1 buffers and amplifies the vco output to a sufficient level to ensure proper counting by the prescaler. Transistor Q1 has a fixed gain of ten, and C15 couples the desired amount of rf into the MCI 2013P. About 0.8-volts p-p of rf is needed at pin 15 of the 12013P to ensure proper counting.

The programmable counter has the responsibility of dividing the vco output into 10-kHz increments over the 299-channe! range when the loop is locked. To do this, the counter has to be designed to divide-by-3500-to-3799 in 299 steps. The following formula shows how the desired counter range was derived: n (number counter divides by) is equal to: (3.5 MHz-3.799 MHz)/1000 Hz.

Dividing each frequency by the 1000-Hz reference yields the desired coverage of the counter. The 1000-Hz frequency is the phase detector sampling frequency or reference frequency. A 1000-Hz reference is needed at the phase detector to provide the 10-kHz step at the vco. This can be proven, as follows, For the moment, assume that the loop is locked and that the counter is set at divide-by-3500. The vco frequency now equals: Fvco is equal to (prescaler)(divide-by-n number)(pha5e detector reference). This yields (10) (3500X1000), or 35 MHz.

If the programmable

FROM SV.'ITCh DECODER

FROM SV.'ITCh DECODER

counter is advanced to MHz. The vco now has in- time the counter is ad-

3501, the vco frequency creased in frequency the vanced one step, now becomes Fvco is equal desired 10 kHz, and it will It should be apparent to (10)(3501X1000) or 3501 increment 10 kHz each that the vco really is given

no choice about the frequency it takes when the loop is locked. When the loop is locked, the programmable counter output will be 1000 Hz and the 4044 phase detector will keep it and the reference in phase on the trailing edge of the two 1000-Hz waveforms. Any phase difference that occurs is used to steer the vco so that it remains locked to the reference. The nature of the loop is to ■ reflect the stability of the low-frequency 1000-Hz reference to the high-frequency vco.

Next, l would like to give some insight into how the programmable counter functions. To begin, let me say that the counter actually counts between two numbers. One number is its maximum or terminal count while the other is a BCD start number. The terminal count is 9999 while the jam set inputs accept the BCD starting count. The BCD starting count comes from the thumbwheel switch decoder. This decoder converts the BCD data from the switches into the proper BCD number for the counters.

When the receiver is set to receive 135.00 MHz, the counter is doing division by

3500. To do this division by 3500, a count of 6499 is loaded into the jam set inputs. This 6499 becomes the counter's starting point. The count load line on the 74196 counters jams in the start count of 6499 and the ICs begin counting to terminal count. It will take 3500 counts to reach the terminal count of 9999. Therefore, the MSB on the last counter is a divide-by-3500 output.

To divide by larger numbers, the starting count is simply made smaller since more counts are needed. When the counter arrives at terminal count, the 7430 NAND gate senses the condition and clears flip-flop U6. This loads the starting number. Upon the next transition of the clock from zero to one, the Q output follows the D input and the counters count to terminal count once more. A sample truth table for one counter is given in Table 1.

This truth table is generated by the thumbwheel switch decoders (Figs. 6 and 7). The decoders drive the 10-kHz, 100-kHz, and the 1-MHz counters. The 10MHz counter has a three hard-wired on its input since it does not change. An interesting feature of the 1-MHz decoder is that it has to change only from five to seven. Since the switch will rotate from zero to nine, the 74150 selectors are wired to insert a five into the counter if an illegal code is selected. If 0,1, 2, 3, 4, 8, or 9 is selected, the synthesizer is operating in the 135 band.

Please remember that when I speak of numbers such as the above 5, 6, or 7, and the hard-wired three, these are numbers to divide by and not the actual counts to be loaded. In the 10-kHz and 100-kHz sections, the thumbwheel switch simply rotates zero to nine. The actual counts loaded here range from zero-loaded for nine to nine-loaded for zero. The examples in Table 2 help illustrate the counter function.

When the counter is at 3799, the 6499 is simply changed to 6200. I have used this counter that I designed, along with variations of it, in many designs. It can operate at quite high speeds as well as perform some strange divide functions.

The next important portion of the synthesizer is the phase detector. This design utilizes the MC4044 phase detector; however, the charge-pump portion is not used. The phase detector generates an error that is related to the phase difference between the 1-kHz reference frequency and the 1kHz output from the programmable counter. The phase detector has a certain gain in volts/radian. This value is known as Kj and was found to be 0.7 volts/radian for the 4044 used here.

The phase detector reference or sampling frequency of 1000 Hz is derived from a stable source. I have used a 10-MHz crystal oscillator as the system standard. The output is simply divided down with simple divide-by-ten stages to the desired frequency of 1 kHz. It is a good idea to build all of the reference frequency generating circuits in a highly shielded enclosure. In my case, the 10 MHz was only 700 kHz away from the receiver i-f so that the shielding was very necessary.

The two outputs from the phase detector are summed together in the loop filter. I use a differential summing loop filter. The loop filter has about a 10-Hz bandwidth, or con. To keep the vco quiet, a two-pole post filter was added. This filter breaks at 50 Hz. It was necessary to keep the loop narrow so that the vco remained fairly pure. Any AM

VCO OUTPUT TO Znà MIXER 35 TO 37 99MHZ

Continue reading here: Vco Suffer Prescaler

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